A HIGH SPEED HAAR TRANSFORM IMPLEMENTATION

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Abstract
This paper presents an implementation of the Haar transform suitable for VLSI integration. It shows how to map a bidimension linear transformation, which has a straightforward multiresolution realization on a pyramid data-parallel computer, onto a pipeline of simple processors. A further simplification of the linear structure leads to an extremely simple implementation based on a two-stage pipeline, capable of processing images as large as 1024×1024 pixels. VLSI simulations with current technologies predict HDTV video rates. Data compression is among the applications that benefit from the new formulation of the transform.

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