Memory-fast interfaces for DRAMs

1 October 1992

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Spectrum

Vol. 29 (10) , 54-57
https://doi.org/10.1109/6.158639

Abstract

The limitations of current nominal 5 V interfaces are examined, and the requirements for interfaces between high-speed DRAMs and processors are outlined. Three solutions are described. One is a center-tap-terminated interface, the second uses Gunning transceiver logic, and the third relies on low-voltage differential signaling.

Keywords

RANDOM ACCESS MEMORY
CMOS TECHNOLOGY
RAIL TO RAIL OUTPUTS
BIPOLAR TRANSISTORS
BICMOS INTEGRATED CIRCUITS
CIRCUIT TESTING
LOGIC DEVICES
LOGIC CIRCUITS
PINS
COSTS

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