An analysis and experimental verification of parasitic oscillations in parralleled power MOSFET's

1 July 1984

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 31 (7) , 959-963
https://doi.org/10.1109/t-ed.1984.21637

Abstract

An analysis of the small signal dynamic model of the power MOSFET is presented which predicts the existence of high-frequency parasitic oscillations when these devices are electrically paralleled. It is shown that the existence of these oscillations is a strong function of the small signal transfer admittance gmand the differential mode drain, gate, and source resistances. The sensitivity of the oscillations to these parameters is determined. Experimental data verifying the qualitative aspects of the analytical results is presented. It is concluded that the problem is potentially most severe for devices which are paralleled by the manufacturer at the chip level. A practical solution to the problem is the introduction of differential mode gate resistance, either as lumped components, or by the use of polysilicon overlays.

Keywords

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