A framework for evaluating design tradeoffs in packet processing architectures

1 January 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 0738100X,p. 880-885
https://doi.org/10.1109/dac.2002.1012746

Abstract

We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.

Keywords

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