FAULTS IN FUZZY LOGIC SYSTOLIC ARRAYS
- 1 September 1990
- journal article
- research article
- Published by Taylor & Francis in Cybernetics and Systems
- Vol. 21 (5) , 513-524
- https://doi.org/10.1080/01969729008902257
Abstract
Systolic VLSI arrays have been proposed for fast fuzzy inference processes in control systems Due to their complexity. VLSI circuits sometimes fail and the result is an erroneous output. In this paper, faults in fuzzy logic systolic arrays are considered. It will be shown that a single fault in the array may complement the fuzzy output. Faults in the fuzzy logic systolic array can be tolerated by either hardware redundancy or time redundancy. The recomputing with shifted operands (RESO) method, time redundancy, and the triple modular redundancy (TMR) method, hardware redundancy, are applied to fuzzy logic systolic array.Keywords
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