Device isolation in high-density LOCOS-isolated CMOS
- 1 June 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 34 (6) , 1337-1345
- https://doi.org/10.1109/t-ed.1987.23089
Abstract
Leakage paths between n- and p-channel devices in high packing density CMOS circuits fabricated using standard LOCOS isolation are investigated. Experimental results and the results of two-dimensional numerical modeling are presented for both a conventional n-well and a retrograde n-well technology. Adequate isolation for 5-V circuit operation is demonstrated for retrograde n-well structures with a 1.8-µm n+to p+diffusion separation, and for conventional n-well structures with a 2.4-µm n+to p+diffusion separation. In both cases, good latchup protection is also demonstrated using thin p-on p+epitaxial material.Keywords
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