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High-speed iterative multiplier
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High-speed iterative multiplier
High-speed iterative multiplier
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D.P. Burton
D.P. Burton
DN
D.R. Noaks
D.R. Noaks
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28 June 1968
journal article
Published by
Institution of Engineering and Technology (IET)
in
Electronics Letters
Vol. 4
(13)
,
262
https://doi.org/10.1049/el:19680200
Abstract
An iterative array is proposed which reduces the multiplication of two binary numbers to one pass through the array and a summation of the outputs produced.
Keywords
SPEED ITERATIVE
MULTIPLIER
HIGH SPEED
BINARY NUMBERS
TWO BINARY
OUTPUTS PRODUCED
ITERATIVE ARRAY
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