A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.Keywords
This publication has 1 reference indexed in Scilit:
- The PowerPC 603 microprocessor: a low-power design for portable applicationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002