A MOS Transistor with self-aligned polysilicon source—drain

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Abstract
A new MOS transistor with self-aligned polysilicon source-drain (SAPSD) is demonstrated. Using a thin implant-doped polysilicon layer above the active channel region, a shallow source-drain junction with negligible leakage is realized. A novel lightly doped-drain (LDD) structure is also incorporated by diffusing dopants from the n+ polysilicon source-drain layer into the silicon substrate, forming the n- region. During the gate oxidation, a sidewall spacer is simultaneously formed by the oxidation of polysilicon source-drain sidewalls. The transistor layout area is saved by bringing the source-drain contacts onto the field oxide region. Experimental results of the new structure are presented.

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