High-resolution low-power CMOS D/A converter

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 2821-2824
https://doi.org/10.1109/iscas.1988.15525

Abstract

A very low-power, high-resolution, medium-speed D/A (digital-to-analog) converter is described. The converter was realized using a standard analog CMOS technology. It achieved 15 bits monotonicity and less than 0.7% overall linearity at a clock frequency of 100 kHz, without requiring any trimming or calibration. The measured SNR (signal-to-noise ratio) was 85 dB, and the measured power dissipation was less than 10 mW.

Keywords

This publication has 3 references indexed in Scilit:

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