Time-Optimal Design of a CMOS Adder
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10586393,p. 186-191
- https://doi.org/10.1109/acssc.1985.671447
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A Regular Layout for Parallel AddersIEEE Transactions on Computers, 1982
- Parallel Prefix ComputationJournal of the ACM, 1980