Hot Electron Reliability Modeling in VLSI Devices

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Abstract
The dependence of hot-electron trapping on device size and applied gate bias is analyzed both theoretically and experimentally. A simple and accurate model is developed to determine the long term stress effect on narrow and short channel devices. It is found that the channel hot electron limit is determined by the emission probability and trap density in the birdsbeak region of narrow devices when the gate bias exceeds the threshold voltage of the parasitic birdsbeak device. The channel lengths, dra-in to source bias and gate oxide trap density for the LOCOS process are essential parameters incorporated in this model. The calculated curves depicting threshold voltage shift versus time are in excellent agreement with empirical data. These shifts are accounted for by the effect of the higher trap density in the birdsbeak region for high bias conditions on narrow devices.

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