Fault Folding for Irredundant and Redundant Combinational Circuits
- 1 November 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-22 (11) , 1008-1015
- https://doi.org/10.1109/T-C.1973.223637
Abstract
Fault folding is the process of applying test equivalent or test implied relations from a primary output towards the connected primary inputs in order to find a reduced set of faults that cover the set of faults on the intervening network.Keywords
This publication has 5 references indexed in Scilit:
- An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic CircuitsIEEE Transactions on Computers, 1971
- Algebraic Fault Analysis for Constrained Combinational NetworksIEEE Transactions on Computers, 1971
- Fault Detection in Redundant CircuitsIEEE Transactions on Electronic Computers, 1967
- On the Necessity to Examine D-Chains in Diagnostic Test Generation—An Example [Letter to the Editor]IBM Journal of Research and Development, 1967
- On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic NetsIEEE Transactions on Electronic Computers, 1966