A 1.5 V circuit technology for 64 Mb DRAMs

1 January 1990

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 17-18
https://doi.org/10.1109/vlsic.1990.111076

Abstract

A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future

Keywords

DRAM CHIPS
VLSI
INTEGRATED CIRCUIT TECHNOLOGY
INTEGRATED MEMORY CIRCUITS
TECHNOLOGICAL FORECASTING

This publication has 1 reference indexed in Scilit:

Trends in megabit DRAM circuit design
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003