An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs
- 1 November 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Consumer Electronics
- Vol. 43 (4) , 1019-1027
- https://doi.org/10.1109/30.642367
Abstract
A new flexible and area-efficient VLSI architecture of a Reed-Solomon product-code decoder/encoder has been developed for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circuit size and decoding latency has the following three features. First, a high area-efficiency has been achieved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, the circuit size and decoding latency has been reduced by using a new architecture to implement the modified Euclid's algorithm. Third, by doubling the internal clock speed (from 18 MHz to 36 MHz), the decoding latency and hence the memory size can be reduced. The decoder/encoder designed by using the proposed method uses a reduced number of gates, by about 30%, than the one based on the conventional architectures.Keywords
This publication has 4 references indexed in Scilit:
- An error-control coding scheme for multispeed play of digital VCRIEEE Transactions on Circuits and Systems for Video Technology, 1995
- Architecture of a high speed Reed-Solomon decoderIEEE Transactions on Consumer Electronics, 1994
- Use of the RS decoder as an RS encoder for two-way digital communications and storage systemsIEEE Transactions on Circuits and Systems for Video Technology, 1994
- On the VLSI design of a pipeline Reed-Solomon decoder using systolic arraysIEEE Transactions on Computers, 1988