Routability-driven fanout optimization

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Abstract
In this paper, we propose an efllcient fanout optimization algorithm which improves circuit performance while honoring an order restriction on the fanouts. This order is derived from a companion placement of mapped circuit. By honoring the place- ment order we generate fanout trees that are free of internal edge crossings, resulting in improved routing and chip area. Our O(n3 ) procedure which is based on an algorithm for constructing optimal alphabetic codes, is optimal for binary trees with monotone tree cost function. For nonbinary trees, we propose a set of rules which reduce size of the solution space while maintaining the optimality. We obtained art average of 149Z0 improvement in chip area without a signifi- cant performance degradation as compared to the SIS fanout optimization tool.

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