A LEARNING PARALLEL ANALOG-TO-DIGITAL VECTOR QUANTIZER

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Abstract
A mixed-mode VLSI architecture for learning vector quantization (LVQ), with on-chip adaptation and dynamic storage of the analog templates, converts analog vectorial data in parallel to digital format. The architecture is digitally configurable, and extends to commonly used algorithms for codebook adaptation besides k-means clustering such as Fuzzy Adaptive Resonance Theory (ART) and Kohonen self-organizing maps. The analog memory and adaptive element of the LVQ cell comprise 6 MOS transistors and one capacitor, and provide for robust self-refresh of the dynamic analog storage. Total cell size including distance and adaptive computations is 80×70 lambda in scalable MOSIS technology. Experimental results from a fabricated 16×16 cell prototype in 2μm CMOS are included.

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