SEM technique for experimentally locating latch-up paths in integrated circuits

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Abstract
A technique is presented for using the scanning electron microscope (SEM) in the electron-beam-induced current (EBIC) mode to delineate latch-up paths in CMOS ICs. In the EBIC mode, the current produced by the collection and separation of the electron-beam-generated electron-hole pairs in the space charge regions of the device is measured and used to form an image. Since the collection of these carriers is dependent on space charge region width (and thus junction potential), anything that alters the depletion layer width will affect the collection efficiency. In a latch condition the junctions involved in the latch will be biased differently from those which are not, and thus the EBIC signal from those regions should be measurably different.

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