SOLID-II: High-voltage high-gain kilo-Ångstrom-channel-length CMOSFET's using Silicide with self-aligned ultrashallow (3S) junction

1 February 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (2) , 260-269
https://doi.org/10.1109/T-ED.1986.22476

Abstract

A simple novel pile-up phenomenon which leads to an available layered structure of silicide with self-aligned ultrashallow (3S) junction is described. Heavily piled-up impurity (P or B) layers less than 50 nm deep under refractory metal (Ti, W, or Pd) silicide accomplish excellent p-n junction characteristics. Good ohmic properties are also obtained with contact resistivity less than 4 × 10-6ω cm2independent of substrate concentration. This notable profile can easily be realized when a high dose (≥ 5 × 1015cm-2) of impurity is implanted not through but into the refractory metal without intermixing, and followed by Silicidation. An application of this new phenomenon for a kilo-Ångstrom-channel-length CMOSFET is also proposed and evaluated using two-dimensional numerical simulation. In the advanced device, silicide on lightly doped drain II (SOLID-II), the breakdown voltage and current gain product of kilo-Ångstrom-channel-length MOSFET's with 3S junction can be significantly improved in comparison with those of conventional LDD devices. In the 0.3-µm-channel-length devices, current gain reduction in SOLID-II is less than 10 percent compared with that in the standard device. However, in the LDD more than a 20-percent reduction is unavoidable with the same breakdown voltage of 8.5 V. It is proved that the SOLID-II: structures can be used very effectively as a 0.2-0.5-µm-channel-length CMOSFET operatable with 5-V power supply.

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