A Realtime Image Signal Processor (Version II) with Micro-Programmable and Expandable Architecture

1 September 1986

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 98-100
https://doi.org/10.1109/esscirc.1986.5468320

Abstract

A micro-programmable Realtime Image Signal Processor (RISP-version II) has been developed fabricated in the 1.5-μm bipolar technology. The RISP-II, designed for use in the local image processing, has attained the per-chip processing speed as high as 100 MIPS. The multi-chip processing has been realized by added features: parallelism with the local image register, and pipelining with the pipeline register. Therefore, the execution speed can easily double or more when two or more RISP-IIs are adopted, and the local window can be enlarged simultaneously.

Keywords

SIGNAL PROCESSING
REGISTERS
IMAGE PROCESSING
ARITHMETIC
PIPELINE PROCESSING
PIXEL
IMAGE SAMPLING
GOLD
DIGITAL IMAGES
IMAGE EDGE DETECTION

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