A 6-ns 256-kbit BiCMOS TTL SRAM

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 24.3/1-24.3/4
https://doi.org/10.1109/cicc.1990.124787

Abstract

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<>

Keywords

BICMOS INTEGRATED CIRCUITS
RANDOM ACCESS MEMORY
DECODING
PULSE AMPLIFIERS
CAPACITANCE
DRIVER CIRCUITS
CITIES AND TOWNS
PULSE CIRCUITS
DELAY EFFECTS
LABORATORIES

This publication has 1 reference indexed in Scilit:

A 7.5-ns 32 K*8 CMOS SRAM
IEEE Journal of Solid-State Circuits, 1988