A CMOS vision chip with SIMD processing element array for 1 ms image processing
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Conventional image processing systems use a video signal as a transmission signal between an image sensor and image processor. The video rate, however, is not fast enough for some applications such as visual feedback for robot control, automobiles, gesture recognition for human interfaces, high speed visual inspection, microscope image processing, and so on. For such applications, the video signal, which is a time-multiplexed signal of pixel data using scanning circuits, is a bottleneck of conventional image processing systems. The key to the realization of high speed and flexible image processing beyond the video signal rate is to remove the bottleneck of data transfer and implement general purpose functionality. In other words, a fully parallel architecture with generality of processing should be adopted instead of scanning circuits. This CMOS vision chip has massively parallel processing elements integrated with photodetectors. These chips have a SIMD massively parallel processing architecture with each processing element (PE) connected to a photodetector (PD) without scanning circuits.Keywords
This publication has 2 references indexed in Scilit:
- High Speed Vision System Using Massively Parallel ProcessingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Optically interconnected parallel computing systemsComputer, 1998