A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A 16-Kb RAM was designed and fabricated using a 0.5- mu m BiCMOS technology. It has a typical address access time of 3.5 ns. The RAM operates at a supply voltage of -4.5 V and features 500-mW power dissipation. A description is given of two techniques crucial to high-speed, low-power design: a wired -OR precoder combined with a low-power, high-speed level converter circuit and a direct column-sensing circuit with a cascode differential amplifier.<>Keywords
This publication has 1 reference indexed in Scilit:
- A 7-ns/350-mW 64-kbit ECL-compatible RAMIEEE Journal of Solid-State Circuits, 1987