Synthesis on multiplexer-based FPGA using binary decision diagrams
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Synthesis on multiplexer-based programmable devices using (ordered) binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An improved synthesis algorithm for multiplexor-based PGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Minimization of binary decision diagrams based on exchanges of variablesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On variable ordering of binary decision diagrams for the application of multi-level logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A good input ordering for circuit verification based on binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- AmapPublished by Association for Computing Machinery (ACM) ,1991
- Technology mapping for electrically programmable gate arraysPublished by Association for Computing Machinery (ACM) ,1991
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986