Flow-through latch and edge-triggered flip-flop hybrid elements

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23 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 138-139
https://doi.org/10.1109/isscc.1996.488543

Abstract

This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.

Keywords

FLIP-FLOPS
CLOCKS
LATCHES
DELAY
AGGREGATES
LOGIC
CIRCUITS
TIMING
FREQUENCY
MASTER-SLAVE

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