A Nine-Valued Circuit Model for Test Generation
- 1 June 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-25 (6) , 630-636
- https://doi.org/10.1109/tc.1976.1674663
Abstract
A nine-valued circuit model for test generation is introduced which takes care of multiple and repeated effects of a fault in sequential circuits. Using this model test sequences can be determined which allow multiple and repeated effects of faults on the internal state of a sequential circuit. Thus valid test sequences are derived where other known procedures, like the D-algorithm, do not find any test although one exists.Keywords
This publication has 3 references indexed in Scilit:
- An Algebraic Model for the Analysis of Logical CircuitsIEEE Transactions on Computers, 1974
- A Heuristic Algorithm for the Testing of Asynchronous CircuitsIEEE Transactions on Computers, 1971
- Hazard Detection in Combinational and Sequential Switching CircuitsIBM Journal of Research and Development, 1965