Verifying equivalence of functions with unknown input correspondence
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Characterization of Boolean functions for rapid matching in EPGA technology mappingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986