A CAD Suite for High-Performance FPGA Design

Abstract
This paper describes the current status of a suite of CAD tools designed specifically for use by designers who are developing high-performance configurable-computing applications. The basis of this tool suite is JHDL [1] a design tool originally conceived as a way to experiment with Run-Time Reconfigured (RTR) designs. However what began as a limited experiment to model RTR designs with Java has evolved into a comprehensive suite of design tools and verification aids with these tools being used successfully to implement high performance applications in Automated Target Recognition (ATR). sonar beamforming and general image processing on configurable-computing systems.

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