A 14 b 100 Msample/s CMOS DAC designed for spectral performance

Abstract

At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.

Keywords

SWITCHES
CLOCKS
DECODING
SWITCHING CIRCUITS
THRESHOLD VOLTAGE
CMOS PROCESS
LINEARITY
OPTICAL WAVELENGTH CONVERSION
CAPACITORS
FREQUENCY

This publication has 2 references indexed in Scilit:

A 12 b accuracy 300 Msample/s update rate CMOS DAC
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A low glitch 14-b 100-MHz D/A converter
IEEE Journal of Solid-State Circuits, 1997