A dual floating point coprocessor with an FMAC architecture
- 23 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 354-355,
- https://doi.org/10.1109/isscc.1996.488714
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A quad-issue out-of-order RISC CPUPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984