A comparative study of unification algorithms for OR-parallel execution of logic languages

1 October 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-34 (10) , 911-917
https://doi.org/10.1109/TC.1985.6312194

Abstract

As a step toward designing a computer architecture suitable for executing parallel logic languages, the author has studied some memory management techniques proposed for creating multiple binding environments, which are required with OR-parallelism. Three algorithms have been implemented using a Prolog-like interpreter and have been tried on some logic programs, to attempt to compare their relative performance. The author describes these algorithms and their implementation and discusses the results of the performance analysis. The attempts compare the algorithms, although accurate comparisons are difficult to make since some aspects of the algorithms are architecture-dependent.

Keywords

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