Abstract
A two-dimensional ferroelectric memory array is combined with a piezoelectric interrogation technique to provide a memory device with nonvolatile storage, random access, non-destructive readout and compatibility with integrated circuits. Binary information is stored as either a positive or negative polarization state in ferroelectric ceramic material and is read out by sensing the polarity of the piezoelectric response of the material. Calculations and experimental results are presented for a 5 word × 5 bits per word prototype device for which a complete logic and driving circuit has been designed and used. Switching characteristics, disturb pulse sensitivity, and changes with temperature are presented. Calculations show that word-to-word capacitive coupling will affect the maximum size of the memory and will probably limit the number of words per chip to approximately 25. No such limit exists on the number of bits per word.

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