Novel switched logic CMOS latch building block

25 April 1985

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 21 (9) , 398-399
https://doi.org/10.1049/el:19850283

Abstract

A six-transistor static CMOS building block for latches is proposed, based on the use of PMOS and NMOS switches. It is shown how latches can be built from this building block.

Keywords

NMOS SWITCHES
LOGIC IC
PMOS SWITCHES
D-LATCH
SIX TRANSISTOR CONFIGURATION
LOGIC DESIGN
BUILDING BLOCK
SWITCHED LOGIC CMOS LATCH

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