A vertical FET with self-aligned ion-implanted source and gate regions
- 1 January 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 25 (1) , 56-57
- https://doi.org/10.1109/t-ed.1978.19031
Abstract
A new self-aligned vertical channel JFET has been fabricated using ion-implantation and LOCOS techniques. This device required four photolithography processes. Fine patterning and accurate mask alignment are not required by this process. The electrical properties of this device are a voltage amplification factor of more than 5, a source-to-gate breakdown voltage of 50 V, and a drain-to-gate breakdown voltage of 140 V. It is possible to realize a larger voltage amplification factor, compared to the diffused vertical FET.Keywords
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