A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS
- 27 October 2003
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 38 (11) , 1866-1875
- https://doi.org/10.1109/jssc.2003.818294
Abstract
This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm/sup 2/ experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.Keywords
This publication has 7 references indexed in Scilit:
- TCP performance re-visitedPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder corePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- End system optimizations for high-speed TCPIEEE Communications Magazine, 2001
- On the effective evaluation of TCPACM SIGCOMM Computer Communication Review, 1999
- End-to-end Internet packet dynamicsIEEE/ACM Transactions on Networking, 1999
- Profiling and reducing processing overheads in TCP/IPIEEE/ACM Transactions on Networking, 1996
- An analysis of TCP processing overheadIEEE Communications Magazine, 1989