Energy Consumption in Digital Optical ICs With Plasmon Waveguide Interconnects
- 27 November 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Photonics Technology Letters
- Vol. 19 (24) , 2036-2038
- https://doi.org/10.1109/LPT.2007.909629
Abstract
Limits on energy consumption in digital optical integrated circuits (ICs) using conventional and plasmon waveguide interconnects are presented. The maximum allowable on-chip power density imposes a lower limit on the spacing between devices and together with clock skew imposes an upper limit on the clock frequency. Optical ICs with low-loss plasmon waveguide interconnects may become viable if plasmon waveguide losses in the range 0.1-0.01 dB/m can be achieved.Keywords
This publication has 7 references indexed in Scilit:
- Energy consumption limits in high-speed optical and electronic signal processingElectronics Letters, 2007
- Metal–Dielectric Slot-Waveguide Structures for the Propagation of Surface Plasmon Polaritons at 1.55 $\mu{\hbox {m}}$IEEE Journal of Quantum Electronics, 2007
- Guided subwavelength plasmonic mode supported by a slot in a thin metal filmOptics Letters, 2005
- Surface plasmon subwavelength opticsNature, 2003
- Nanophotonics: design, fabrication, and operation of nanometric devices using optical near fieldsIEEE Journal of Selected Topics in Quantum Electronics, 2002
- Is interconnect the weak link?IEEE Circuits and Devices Magazine, 1998
- Optics for low-energy communication inside digital processors: quantum detectors, sources, and modulators as efficient impedance convertersOptics Letters, 1989