Experimental x-ray process latitude evaluation using E-D tree analysis

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Abstract
An E-D tree based analysis of experimental X-ray lithography data is presented for features characteristic of CMOS logic gate levels. Pattern-specific print biases for isolated lines (150- 250 nm) and two types of nested lines (250 nm) are characterized. Depths of gap for increasing exposure latitudes at +/- 20 nm line width control are calculated for individual features. common process window analysis is performed on the nested and isolated 250-nm patterns. The impact of reducing the nominal mask to wafer gap (35-26 micrometers ) on maximum exposure latitude is evaluated and the effect of gap reduction and overexposure on the nested to isolated print bias is examined.

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