SAC: a systolic array controller chip
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
SAC (systolic array controller) is a chip designed for use with an NCR 16-bit fixed-point multiplier/accumulator (MAC) chip to form a two-chip cell in systolic arrays for signal processing applications. The SAC/MAC cell can be used as an inexpensive, flexible building block for either one-dimensional or two-dimensional systolic arrays in either application-specific or general-purpose machines. The SAC provides an interface to other cells via four parallel ports. It routes data to and from the companion high-speed MAC via one 16-bit bidirectional port, controls the MAC, and provides 64 words of scratchpad memory for programs and data.Keywords
This publication has 3 references indexed in Scilit:
- Warp architecture and implementationACM SIGARCH Computer Architecture News, 1986
- An interactive system for VLSI chip physical designIBM Journal of Research and Development, 1984
- Design of the PSC: A Programmable Systolic ChipPublished by Springer Nature ,1983