Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool
- 1 December 1995
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the 39th conference on Design automation - DAC '02
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- HYPER-LP: a system for power minimization using architectural transformationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1992
- A Method for the Construction of Minimum-Redundancy CodesProceedings of the IRE, 1952