Fault-tolerant schemes for parallel architectures

22 October 1987

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 23 (22) , 1206-1207
https://doi.org/10.1049/el:19870839

Abstract

Fault-tolerance schemes for efficient implementation in parallel VLSI processors are discussed, and a modular approach for tree and mesh-structured architectures is described

Keywords

EFFICIENT IMPLEMENTATION
FAULT TOLERANT COMPUTING
MODULAR APPROACH
PARALLEL VLSI PROCESSORS
MESH-STRUCTURED ARCHITECTURES
PARALLEL ARCHITECTURES

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