Field programmable gate arrays and floating point arithmetic

1 September 1994

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Vol. 2 (3) , 365-367
https://doi.org/10.1109/92.311646

Abstract

We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.

Keywords

This publication has 2 references indexed in Scilit:

An architecture for electrically configurable gate arrays
IEEE Journal of Solid-State Circuits, 1989
A Proposed Standard for Binary Floating-Point Arithmetic
Computer, 1981