The formal description and verification of hardware timing
- 1 July 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 40 (7) , 811-826
- https://doi.org/10.1109/12.83619
Abstract
A formalism in which timing properties of digital hardware may be specified, derived, and formally verified is introduced as a rigorous theory for hardware timing. A rigorous modeling framework has been used to create a family of related verification techniques rather than a single timing analysis tool. This framework is based on a model of interacting finite state machines called CIRCAL, a formalism developed for the purpose of describing and validating complex concurrent systems. In this approach to hardware timing analysis, the presence of a composition operator is all-pervasive. It provides a single, uniform mechanism for describing the behavior of interacting hardware modules and for establishing and describing the timing properties of such modules.Keywords
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