Design of hardware efficient selftimed circuits

7 January 1993

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 29 (1) , 6-7
https://doi.org/10.1049/el:19930004

Abstract

One objection to selftimed circuits has been the overhead of hardware required to implement the control circuitry. In the Letter an alternative approach to the implementation of selftimed circuit elements is proposed. By using an alternative CMOS logic family, the enable/disable CMOS differential logic (ECDL), instead of the dynamic cascoded voltage switch logic (DCVSL) to build selftimed blocks, the amount of overhead is reduced. Moreover, because ECDL is static, there is no minimum timing constraint to satisfy in comparison with selftimed systems that use DCVSL. An example of a first-in first-out (FIFO) memory is used to illustrate the technique.

Keywords

This publication has 2 references indexed in Scilit:

Introduction
Published by Springer Nature ,1991
Synchronization Design for Digital Systems
Published by Springer Nature ,1991