High frequency wide range CMOS analogue multiplier

19 November 1992

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 28 (24) , 2228-2229
https://doi.org/10.1049/el:19921431

Abstract

A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2μm process parameters are given. The circuit has an input range of ±4V and linearity error less than 1% for inputs up to ±3V. The magnitude and phase response are very flat; even at 30MHz the change in the magnitude is less than 0.086dB (1%) and the phase shift is less than 5°.

Keywords

MOSIS
SIGNAL PROCESSING
LINEARITY ERROR
INPUT RANGE
INFORMATION PROCESSING
FOUR-QUADRANT MULTIPLIER CIRCUIT
PHASE SHIFT
CMOS ANALOGUE MULTIPLIER
PHASE RESPONSE
WIDE RANGE
HIGH FREQUENCY

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