Module selection for pipelined synthesis
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). The authors give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs for pipelined designs is used to formulate the problem, and an overview of the solution technique is given. Complexities introduced by nonoptimal designs and user constraints are addressed. The results have been validated using designs generated by an automated pipeline synthesis program.Keywords
This publication has 6 references indexed in Scilit:
- Sehwa: a software package for synthesis of pipelines from behavioral specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Predicting area-time tradeoffs for pipelined designPublished by Association for Computing Machinery (ACM) ,1987
- Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral DescriptionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- MAHA: A Program for Datapath SynthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- PLEST: A Program for Area Estimation of VLSI Integrated CircuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital LogicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983