Formation and electrical effects of process induced dislocations in HgCdTe

Abstract
This study provides quantitative assessments of both the stress levels required to form dislocations in HgCdTe and the effect of these process induced dislocations on metal–insulator semiconductor device performance. Unlike previous millimeter size stress‐strain measurements, this study determined the yield stress of HgCdTe on the scale of microns by performing defect etches beneath lithographically defined, high stress films. Both the magnitude and temperature dependence of the microyield stress appear to be similar to macroyield stress values found in the literature. The ability to lithographically define dislocated regions with high stress discontinuous films was used to produce test structures with variable dislocation densities and distributions. The electrical effects of process induced dislocations in these test structures provide insight into the defect production and dark current mechanisms of dislocations. Specifically, dislocations appear to increase the donor and Hg interstitial‐like concentrations in addition to the thermally activated, trap assisted tunneling. The effects of dislocations on array performance were also investigated.

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