Floating CMOS resistor

4 February 1993

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 29 (3) , 306-307
https://doi.org/10.1049/el:19930209

Abstract

A floating resistor scheme is described in which a CMOS device is linearised by the application of a suitably scaled common-mode signal to the gate terminal only. SPICE studies indicate that the proposed resistor offers low distortion over a tuning range of 3:1. The design, for which a patent application has been filed, makes no special demands on device aspect ratios and could offer an economic alternative to fully-balanced topologies.

Keywords

CMOS DEVICE
TUNING RANGE
SPICE STUDIES
GATE TERMINAL
SCALED COMMON-MODE SIGNAL
ASPECT RATIOS
FLOATING RESISTOR SCHEME

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