A hardware FPGA implementation of a 2D median filter using a novel rank adjustment technique
- 1 January 1999
- proceedings article
- Published by Institution of Engineering and Technology (IET)
- Vol. 1999, 103-106
- https://doi.org/10.1049/cp:19990290
Abstract
This paper presents the design and implementation on a Field Programmable Gate Array (FPGA) of a 2-D median filter, which is capable of obtaining a median value every clock cycle. The device is designed to operate in rear-time with rates of over 80 megasamples per second on n-bit sample sequences. Also, the operation speed remains constant regardless of the size of the selected mask NKeywords
This publication has 0 references indexed in Scilit: