Computer Redundancy: Design, Performance, and Future

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Abstract
The literature on the theoretical aspects of redundancy in digital computers is extensive providing a sound basis for highly reliable design. This paper describes the design problems, the reliability prediction, the field performance, and the future application of redundancy techniques to digital systems. Triple modular redundancy (TMR) is described using the logic of the Launch Vehicle Digital Computer utilized in the uprated Saturn I and the Saturn V vehicles. The self-correcting memory of this computer is described along with the associated design problems and the design verification based on production experience. Consideration is given to system design problems involved with TMR logic. A Monte Carlo technique for predicting computer reliability is considered in a design engineering rather than programmer approach. The unique means of indicating single-channel malfunctions, while continuing to mask these single-channel malfunctions with respect to system operation, is introduced. The result of field operation are given and compared with predicted reliability. Quad redundancy at the component part level is described using the circuitry of the primary processor and data storage (PPDS) for NASA's Orbital Astronomical Observatory. The process of arriving at a quad redundancy implementation is considered in light of the constraints of cost, schedule, and an initial reliability requirement of 95 percent for a year's operation in space. The circuit and system design problems associated with quad redundancy such as impedance and part parameter variations, power consumption, fan out limitations, and testing restrictions are indicated. The results of field operation are given and compared with predicted reliability.

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