The module controller chip (MCC) of the ATLAS pixel detector

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Abstract
The ATLAS pixel detector is organized in 3 barrels and 5 forward and backward disks. The basic building block for each of those detector components is the detector module. There are a total of 2,228 of them, each one having 16 analog front-end (FE) chips, bump-bonded to individual diodes of a silicon detector, and a module controller chip (MCC). There are 61,440 channels in a module for an active area 16/spl times/64 mm/sup 2/ which are controlled and read out by a MCC. Therefore in total there are 1.4/spl times/10/sup 8/ channels to be read out the whole detector. Main LHC constraints are 40 MHz bunch crossing, 75 kHz Level 1 trigger rate, 2.5 /spl mu/s Level 1 trigger latency and a dose of 300 kGy (1/spl times/10/sup 15/ cm/sup -2/ 1 MeV neutron equivalent fluence), for the innermost barrel. The MCC described in this paper is a non rad-hard version which is used for the ATLAS pixel demonstrator program.

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